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| author | Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> | 2021-11-04 19:35:31 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-05 12:57:42 +0000 |
| commit | 70701eba8db6604b55320fa30b46be5046421fa5 (patch) | |
| tree | 5273f08a6afefdabf4eb9cf81f23d0029d65f9c9 /spd/lp5/memory_parts.json | |
| parent | d74f6f5a5d0a95e4c3b499ae730ef98c7a8260cd (diff) | |
mb/google/taeko: Update the FIVR configurations
This patch sets the enable the external voltage rails since taeko
board have V1p05 and Vnn bypass rails.
BRANCH=None
BUG=b:204832954
TEST=FW_NAME=Check in FSP log and run PLT test
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'spd/lp5/memory_parts.json')
0 files changed, 0 insertions, 0 deletions