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| author | Nico Huber <nico.h@gmx.de> | 2024-05-31 18:18:48 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-11 09:17:11 +0000 |
| commit | 391ba65a9e1150ff594c881003dfebcdd18b8aba (patch) | |
| tree | c7e6807b4abbaf29b79959a8b0033a28129918ec /spd/ddr4/set-0/spd-1.hex | |
| parent | 003d6397c6237e618e846b655283bdb9c605c518 (diff) | |
cpu/via: Implement cache as RAM
The overall procedure is taken from the original code that was removed
in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the
start and end was updated (expect timestamp and BIST result in `xmm*'
registers), stack is aligned to 16B, and linker symbols are now used
for the CAR and cached XIP ranges.
Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82766
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'spd/ddr4/set-0/spd-1.hex')
0 files changed, 0 insertions, 0 deletions