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| author | Chia-Ling Hou <chia-ling.hou@intel.com> | 2023-05-15 17:31:57 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-19 10:16:36 +0000 |
| commit | 141d0dfafb211185f97460cf5d5e5f3e81f06c3d (patch) | |
| tree | ca1a9a85e235cc581d5871d91cb92b20bb6cfd56 /spd/ddr4/memory_parts.json | |
| parent | ede5564b3e3ee082c93f915a902d98d064a11950 (diff) | |
soc/intel/jasperlake: Add PsysPmax config
Enable PSYS capability. PSYS is required to safeguard the system
stability if no charger IC.
BUG=b:281479111
TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196
Reviewed-by: Reka Norman <rekanorman@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'spd/ddr4/memory_parts.json')
0 files changed, 0 insertions, 0 deletions