nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change

When more than one DIMM is installed on a DCT, only the first DIMM
delay values are scaled to the new memory clock frequency after a
memory clock change during write leveling.

Store the previous memory clock of each DIMM during write leveling
to ensure that every DIMM has its delay values rescaled.

Change-Id: I56e816d3d3256925598219d92783246f5f4ab567
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14479
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>

0 files changed, 0 insertions, 0 deletions