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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-06-26 14:15:57 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-15 02:44:36 +0100
commitf3aa375f44531ca4a504186d76e69b6d07dc4ae7 (patch)
tree211d71c562a131f5bc3c713493d48d8969718017 /payloads
parentb7a8b8c6fb4a8b76942e1d8d1885c6f817376b65 (diff)
northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
The existing code did not set Rtt timing parameters when registered DIMMs were used with Family 15h processors. Set the Rtt values according to the BKDG recommendations. Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12010 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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