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authorSean Rhodes <sean@starlabs.systems>2022-07-04 21:44:32 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-07-13 10:45:12 +0000
commit5a26d817f79089081c0727fa12d4cfb27033c13a (patch)
tree409a32c21959f657103dd516f36c2de9ef8748d3 /payloads
parent207225c68619d4f4c24138454fd2b622ea76dd47 (diff)
payloads/tianocore: Hook up PCI Express Base Address and Length
Hook up edk2 build options PCIE_BASE_ADDRESS and PCIE_BASE_LENGTH to CONFIG_ECAM_MMCONF_BASE_ADDRESS and CONFIG_ECAM_MMCONF_LENGTH. This patch has been reviewed upstream but not yet merged (2022/07/08). It won't cause any problems for any existing branches or forks that do not have this build option hooked up. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie5d50cc4619354d3c98adf6cde12c192be759869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'payloads')
-rw-r--r--payloads/external/Makefile.inc1
-rw-r--r--payloads/external/tianocore/Makefile8
2 files changed, 9 insertions, 0 deletions
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index e560cbe71a..3749b9e504 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -180,6 +180,7 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
+ CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
index 7dcaf201b3..d7f03bf0b9 100644
--- a/payloads/external/tianocore/Makefile
+++ b/payloads/external/tianocore/Makefile
@@ -44,6 +44,14 @@ endif
ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
endif
+# PCIE_BASE_ADDRESS = 0
+ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
+BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
+endif
+# PCIE_BASE_LENGTH = 0
+ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
+BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH)
+endif
# PRIORITIZE_INTERNAL = FALSE
ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE