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authorAaron Durbin <adurbin@chromium.org>2015-07-24 17:10:31 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-07-29 19:31:07 +0200
commit7f78849fc70879737260739034af4b2a99513e4d (patch)
treeb26830bf803930807c64f60f3479ec0a1cecca47 /payloads
parent8dfa660a68be3e5268c78f2a6e6643795beed76f (diff)
skylake: align power management names with hardware
Some of the field and register names in the power management code were not reflecting current chipset documentation. While in there fix 0-sized array in the power_state structure. Lastly, log the entire STD GPE register for visibility in elog. It reports as an extension of other GPIO wake events. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288296 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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