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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-01-25 21:46:10 +1100
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-02-16 04:51:47 +0100
commit6e56de3d202c2175a13c91ab2c1bc1eb0d7f652a (patch)
tree7747e78113ebd580e23440d7c29634ad5610bd59 /payloads/tianocoreboot
parent4726a87c9a615dc26733cd799f8c4b78670f9ae7 (diff)
Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
Step 2: change the Persimmon code to adapt it to the new board's hardware. The NF81-T56N-LF is a IPC form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) APU - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V) - VGA and LVDS (via Analogix ANX3110) - AMD A55E (Hudson-E1) southbridge - 6x USB 2.0/1.1 ports - 5x SATA3 6Gb/s, 1x mSATA socket - 6-Channel HD Audio (via VIA VT1705) - PCI and ISA (via ITE IT8888)?? - NEC uPD78F0532 microcontroller on I2C ("SEMA")?? - 2x RJ45 GbE (via Realtek RTL8111E x2) - Fintek F71869AD Super I/O - PS/2 KB/MS port - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver) - GPIO header - CIR header - 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS) Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies* claiming the SPI flash is 16MB. They also use red pen over the chip so you wont see this deceit. Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4801 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'payloads/tianocoreboot')
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