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author | Julius Werner <jwerner@chromium.org> | 2019-08-12 16:45:21 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-22 10:36:22 +0000 |
commit | db7f6fb75282a305c2b0f5540d2f7be939f20dde (patch) | |
tree | 2c4fc9e51c6c38c9d7a10a91083c961fd914471e /payloads/nvramcui/nvramcui.c | |
parent | 54ff1a0ad3bb3c1c4bc5283aaf2f03b17c3b25f1 (diff) |
Add buffer_to/from_fifo32(_prefix) helpers
Many peripheral drivers across different SoCs regularly face the same
task of piping a transfer buffer into (or reading it out of) a 32-bit
FIFO register. Sometimes it's just one register, sometimes a whole array
of registers. Sometimes you actually transfer 4 bytes per register
read/write, sometimes only 2 (or even 1). Sometimes writes need to be
prefixed with one or two command bytes which makes the actual payload
buffer "misaligned" in relation to the FIFO and requires a bunch of
tricky bit packing logic to get right. Most of the times transfer
lengths are not guaranteed to be divisible by 4, which also requires a
bunch of logic to treat the potential unaligned end of the transfer
correctly.
We have a dozen different implementations of this same pattern across
coreboot. This patch introduces a new family of helper functions that
aims to solve all these use cases once and for all (*fingers crossed*).
Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'payloads/nvramcui/nvramcui.c')
0 files changed, 0 insertions, 0 deletions