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authorDuncan Laurie <dlaurie@chromium.org>2013-05-29 15:27:55 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-25 23:55:15 +0100
commit2d9d39a7041cf531246845194f76cb9f65eaa08d (patch)
tree51f60a7d9ede4ee6f2b44e270d85a08195dd6aef /payloads/libpayload
parent5afca1357fdaebc5c4ad2b2a963f3c239648ba76 (diff)
lynxpoint: Enable USB clock gating, late setup, and sleep prep
Both EHCI and XHCI controllers have additional setup steps that are not part of the PEI reference code so they need to be done later. Both controllers also have specific clock gating setup requirements that are now implemented. Additionally they both have specific requirements when entering sleep states. XHCI needs something in S3/S4/S5 and EHCI only has steps for S4/S5 entry. Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57033 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4217 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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