soc/intel/cannonlake: Set correct serirq mode

Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.

This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.

Tested on system76 galp3-c, out-of-tree WHL-U board

Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>

0 files changed, 0 insertions, 0 deletions