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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-11-25 02:21:57 -0800
committerFurquan Shaikh <furquan@google.com>2020-12-08 22:57:54 +0000
commit4eb489fb0f2d2ca3a1da2ad3ca0f608d503182ee (patch)
treecca4a76fb4fbd55f02ab5cc4afc539bb0aea900d /payloads/libpayload/libcbfs/Makefile.inc
parent237afda813c87fa65cb2adf2df9e7368d0479034 (diff)
soc/intel/common/fast_spi: Add support for configuring MTRRs
This change enables caching for extended BIOS region. Currently, caching is enabled for the standard BIOS region upto a maximum of 16MiB using fast_spi_cache_bios_region, used the same function to add the support for caching for extended BIOS region as well. Changes include: 1. Add a new helper function fast_spi_cache_ext_bios_window() which calls fast_spi_ext_bios_cache_range() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map and checks for allignment and set mtrr. 2. Make a call to fast_spi_cache_ext_bios_region() from fast_spi_cache_bios_region (). 3. Add new helper function fast_spi_cache_ext_bios_postcar() which does caching ext BIOS region in postcar similar to 1. 4. If the extended window is used, then it enables caching for this window similar to how it is done for the standard window. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47991 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/libcbfs/Makefile.inc')
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