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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-16 00:18:19 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-18 06:03:39 +0000 |
| commit | 0e7c519546f1545f35102c9cf61fcbae88cf5e8c (patch) | |
| tree | 00a21fe542be0a59ae8090943f1ac8f0f49a18ea /payloads/libpayload/libc | |
| parent | 8bbff1f55494db50b92306a5f65c634c87e9c9d7 (diff) | |
soc/intel/jasperlake: Make use of FSP_ARRAY_LOAD macro
Add FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ia20cabcaf9724882c68633eb9b510230e993768c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'payloads/libpayload/libc')
0 files changed, 0 insertions, 0 deletions