diff options
| author | Hsin-Te Yuan <yuanhsinte@google.com> | 2022-08-09 15:00:55 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-09-01 14:21:11 +0000 |
| commit | cb28d649eab01a43eb28b95ac69631c4261ccfae (patch) | |
| tree | 47e50bc095223d64eadf852fe317c1312f4d9a17 /payloads/libpayload/include | |
| parent | 412222ae75d1743a78d2b745754431a558f31be8 (diff) | |
x86/cache.c: Implement dcache_*
A new ChromeOS automated test will be introduced to check the cbmem log
of diagnostic boot mode. Because the diagnostic boot does not allow
booting into kernel, the test must perform AP reset and then check the
cbmem log afterwards. However, the memory content might not be written
back to memory (from CPU cache) during AP reset because of the cache
snooping mechanism on x86. Hence, some API to flush cache is needed.
Implement dcache_* to allow flushing cache proactively in x86. To avoid
unnecessary flush, check dma_coherent before calling dcache_* functions,
which will be always true in x86. Therefore, this change won't affect
the original functionality.
BUG=b:190026346
TEST=FW_NAME=primus emerge-brya libpayload
Cq-Depend: chromium:3841252
Signed-off-by: Hsin-Te Yuan <yuanhsinte@google.com>
Change-Id: I622d8b1cc652cbe477954a900885d12e6494d94d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'payloads/libpayload/include')
| -rw-r--r-- | payloads/libpayload/include/x86/arch/cache.h | 18 | ||||
| -rw-r--r-- | payloads/libpayload/include/x86/arch/cpuid.h | 19 |
2 files changed, 31 insertions, 6 deletions
diff --git a/payloads/libpayload/include/x86/arch/cache.h b/payloads/libpayload/include/x86/arch/cache.h index 22e5940962..8c915c34fb 100644 --- a/payloads/libpayload/include/x86/arch/cache.h +++ b/payloads/libpayload/include/x86/arch/cache.h @@ -31,15 +31,21 @@ #ifndef __ARCH_CACHE_H__ #define __ARCH_CACHE_H__ +#include <stddef.h> +#include <stdint.h> + +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + +void dcache_invalidate_all(void); +void dcache_clean_invalidate_all(void); +void dcache_clean_all(void); +void dcache_clean_by_mva(void const *addr, size_t len); +void dcache_invalidate_by_mva(void const *addr, size_t len); +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); /* NOOPs mirroring ARM's cache API, since x86 devices usually cache snoop */ #define dmb() #define dsb() -#define dcache_clean_all() -#define dcache_clean_by_mva(addr, len) -#define dcache_invalidate_all() -#define dcache_invalidate_by_mva(addr, len) -#define dcache_clean_invalidate_all() -#define dcache_clean_invalidate_by_mva(addr, len) #define cache_sync_instructions() #endif diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index ddd606a072..b01646dac0 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -47,6 +47,25 @@ _declare_cpuid(edx) #undef _declare_cpuid +#define cpuid_sub_leaf(fn, sub_leaf, eax, ebx, ecx, edx) \ + asm("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "0"(fn), "1"(sub_leaf)) + +#define _declare_cpuid_sub_leaf(reg) \ + static inline unsigned int cpuid_sub_leaf_##reg( \ + unsigned int fn, unsigned int sub_leaf) \ + { \ + unsigned int eax, ebx, ecx, edx; \ + cpuid_sub_leaf(fn, sub_leaf, eax, ebx, ecx, edx); \ + return reg; \ + } + +_declare_cpuid_sub_leaf(eax) +_declare_cpuid_sub_leaf(ebx) +_declare_cpuid_sub_leaf(ecx) +_declare_cpuid_sub_leaf(edx) + +#undef _declare_cpuid_sub_leaf + static inline unsigned int cpuid_max(void) { return cpuid_eax(0); |