diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-02-10 11:01:49 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-02-19 19:50:25 +0100 |
commit | 152e5a03a130cea3009685cbf7eb0ea354d9fd1c (patch) | |
tree | d84669468988416d9d37f15c54d5db3343363cd5 /payloads/libpayload/include | |
parent | e0969aec2573872b9f528e33edd2cf3fb84c5948 (diff) |
libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
using get_cpu_speed().
Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13671
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'payloads/libpayload/include')
-rw-r--r-- | payloads/libpayload/include/coreboot_tables.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 24cbf453eb..276f25fe89 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -268,6 +268,14 @@ struct cb_boot_media_params { uint64_t boot_media_size; }; +#define CB_TAG_TSC_INFO 0x0032 +struct cb_tsc_info { + uint32_t tag; + uint32_t size; + + uint32_t freq_khz; +}; + #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 |