armv7: add wrappers to read/write L2ACTLR

This adds inline wrappers to read the L2 cache auxiliary control
register (L2ACTLR).

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f
Reviewed-on: https://gerrit.chromium.org/gerrit/64861
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4437
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 15 insertions, 0 deletions

diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h
index 2928d10017..0414da37f2 100644
--- a/payloads/libpayload/include/armv7/arch/cache.h
+++ b/payloads/libpayload/include/armv7/arch/cache.h
@@ -240,6 +240,21 @@ static inline void write_l2ctlr(uint32_t val)
 	isb();
 }
 
+/* read L2 Auxiliary Control Register (L2ACTLR) */
+static inline uint32_t read_l2actlr(void)
+{
+	uint32_t val = 0;
+	asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
+	return val;
+}
+
+/* write L2 Auxiliary Control Register (L2ACTLR) */
+static inline void write_l2actlr(uint32_t val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
+	isb();
+}
+
 /* read system control register (SCTLR) */
 static inline uint32_t read_sctlr(void)
 {