diff options
| author | Yunzhi Li <lyz@rock-chips.com> | 2015-06-19 17:09:04 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-06 09:40:02 +0200 |
| commit | aa33609d289c4ee07ec10e4825bc055492fa107c (patch) | |
| tree | 1ef5470236076ecd703ec52dd1a33a00c1fc88f7 /payloads/libpayload/drivers/usb/dwc2_private.h | |
| parent | 394933640bc0515617117ed0cb8de7702bc9c1bf (diff) | |
libpayload: usb: dwc2: support interrupt transfer
dwc2 host core do not have a periodic schedule list, so try to send
an interrupt packet in poll_intr_queue() function and use frame
number read from usb core register to calculate time and schedule
transfers.
BUG=None
TEST=Tested on RK3288 with two USB keyboards(connect to SoC without
USB hub), both work correctly.
BRANCH=None
Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157
Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280750
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/drivers/usb/dwc2_private.h')
| -rw-r--r-- | payloads/libpayload/drivers/usb/dwc2_private.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h index 7e6621dce8..c1090420ec 100644 --- a/payloads/libpayload/drivers/usb/dwc2_private.h +++ b/payloads/libpayload/drivers/usb/dwc2_private.h @@ -24,9 +24,18 @@ typedef struct dwc_ctrl { #define DMA_SIZE (64 * 1024) void *dma_buffer; - uint32_t *hprt0; + u32 *hprt0; + u32 frame; } dwc_ctrl_t; +typedef struct { + u8 *data; + endpoint_t *endp; + int reqsize; + u32 reqtiming; + u32 timestamp; +} intr_queue_t; + #define DWC2_INST(controller) ((dwc_ctrl_t *)((controller)->instance)) #define DWC2_REG(controller) ((dwc2_reg_t *)((controller)->reg_base)) |