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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-31 21:44:05 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-06-05 13:05:03 +0000 |
| commit | ef53634d9a68c93b123f792dc4a0336346b82b8c (patch) | |
| tree | bce33bea71913bbd87214617b6aec7a946cdc457 /payloads/libpayload/drivers/serial/qcs405.c | |
| parent | d2644dbf5fc1259c7bfcdbe3be9831e97d10d62e (diff) | |
mb/google/cherry: Get RAM code from ADC
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Cherry the RAM code can be
read from ADC channel 2 and 3.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'payloads/libpayload/drivers/serial/qcs405.c')
0 files changed, 0 insertions, 0 deletions