diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-26 13:34:37 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-29 20:10:14 +0100 |
| commit | a09760eb451466c7972614ef9d73752e16a1bf69 (patch) | |
| tree | 64a97a894065e2cd4fbc63882b65d35eb8313afa /payloads/libpayload/arch | |
| parent | bc07f5d93552640793254ce003937ec646120a21 (diff) | |
libpayload: add x86 ROM variable MTRR support
On x86, coreboot may allocate a variable range MTRR for enabling caching
of the system ROM. Add the ability to parse this structure and add the
result to the sysinfo structure.
An example usage implementation would be to obtain the variable MTRR
index that covers the ROM from the sysinfo structure. Then one would
disable caching and change the MTRR type from uncacheable to
write-protect and enable caching. The opposite sequence is required
to tearn down the caching.
Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch')
| -rw-r--r-- | payloads/libpayload/arch/x86/coreboot.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index f4f9b86f9e..6c6122d26c 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -158,6 +158,12 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif +static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) +{ + struct cb_x86_rom_mtrr *rom_mtrr = ptr; + info->x86_rom_var_mtrr_index = rom_mtrr->index; +} + static void cb_parse_string(unsigned char *ptr, char **info) { *info = (char *)((struct cb_string *)ptr)->string; @@ -281,6 +287,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; + case CB_TAG_X86_ROM_MTRR: + cb_parse_x86_rom_var_mtrr(ptr, info); + break; } ptr += rec->size; @@ -294,7 +303,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + int ret; + + /* Ensure the variable range MTRR index covering the ROM is set to + * an invalid value. */ + info->x86_rom_var_mtrr_index = -1; + + ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); if (ret != 1) ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); |