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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-04 01:41:23 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 17:49:50 +0000 |
| commit | 85d98d9236c006e6ea328e8cde79b5bc15ee1264 (patch) | |
| tree | e1003bcf29ceb23545cdf3cb8dacf117f3b9c847 /payloads/libpayload/arch/mips/cache.c | |
| parent | 62bef5a6bebbb01f00fd3f11488db749b005087e (diff) | |
nb/intel/haswell: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Diffstat (limited to 'payloads/libpayload/arch/mips/cache.c')
0 files changed, 0 insertions, 0 deletions