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authorJulius Werner <jwerner@chromium.org>2016-08-05 21:27:47 -0700
committerAaron Durbin <adurbin@chromium.org>2016-08-13 02:46:19 +0200
commit1143d08f7e0a5c203312f054a08301445cafdec8 (patch)
tree469ada8209572fb7442e03341dc7b47ca9686bb0 /payloads/libpayload/arch/arm
parent55ffccfbaea62c4c8e5a69c8956441758d657eb1 (diff)
libpayload: head.S: Avoid clearing BSS (and heap) again
3 out of 4 architectures currently zero out the payload BSS in early assembly code, which is pointless since the code loading the payload has already done that (with a more efficient memset). ARM64 has never had any code like this and can run just fine without it. This also defeats the new optimization of moving the heap out of the BSS, since all three implementations assume that everything between _edata and _end is BSS. We should just take this out. Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/arm')
-rw-r--r--payloads/libpayload/arch/arm/head.S19
1 files changed, 0 insertions, 19 deletions
diff --git a/payloads/libpayload/arch/arm/head.S b/payloads/libpayload/arch/arm/head.S
index 788e328322..299faf2c4f 100644
--- a/payloads/libpayload/arch/arm/head.S
+++ b/payloads/libpayload/arch/arm/head.S
@@ -33,22 +33,6 @@
* Our entry point
*/
ENTRY(_entry)
-
- /* TODO: disable interrupts */
-
- /* Clear BSS */
- mov r12, #0
- ldr r2, bss_boundaries
- ldr r3, bss_boundaries + 4
- cmp r2, r3
- beq no_bss
-
- sub r3, #4 /* Account for late condition check. */
-loop:
- cmp r2, r3
- str r12, [r2], #4
- blt loop
-no_bss:
/* Save off the location of the coreboot tables */
ldr r1, 1f
str r0, [r1]
@@ -70,9 +54,6 @@ no_bss:
ENDPROC(_entry)
.align 4
-bss_boundaries:
- .word _edata
- .word _end
1:
.word cb_header_ptr
2: