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authorYidi Lin <yidilin@chromium.org>2024-05-24 12:15:11 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-06-05 11:08:48 +0000
commit628b8ed549ce109ab01617d62d74891b07fedf31 (patch)
tree1f9587edeb5b207f9f1417db28a06493852fc54c /payloads/libpayload/arch/arm64/cpu.S
parentd1459792a694e85e566ad008256bf64dc9f9f7b1 (diff)
arch/arm64: Support FEAT_CCIDX
ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented. If numsets and associativity from CCSIDR_EL1 are not correct, the system would hang during mmu_disable(). Rather than assuming that FEAT_CCIDX is not implemented, this patch adds a check to dcache_apply_all to use the right register format. Reference: - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770 BUG=b:317015456 TEST=mmu_disable works on the FEAT_CCIDX supported SoC. TEST=manually add mmu_disable to emulation/qemu-aarch64/bootblock.c and verify with the command qemu-system-aarch64 -bios \ ./coreboot-builds/EMULATION_QEMU_AARCH64/coreboot.rom -M \ virt,secure=on,virtualization=on -cpu max -cpu cortex-a710 \ -nographic -m 8192M Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82635 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'payloads/libpayload/arch/arm64/cpu.S')
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