diff options
| author | Julius Werner <jwerner@chromium.org> | 2020-02-14 12:42:01 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:42:34 +0000 |
| commit | bf33b03acf27d79df9bf1bd8d5075b70196b1844 (patch) | |
| tree | 403c22abdb570c0956ce6655ab49dc8b7ce5f9a1 /payloads/libpayload/arch/arm64/cpu.S | |
| parent | 6cf33858b64449ad6e22cd27ec5734a972b8f39e (diff) | |
libpayload: arm64: Keep instruction cache enabled at all times
This patch makes libpayload enable the instruction cache as the very
first thing, which is similar to how we treat it in coreboot. It also
prevents the icache from being disabled again during mmu_disable() as
part of the two-stage page table setup in post_sysinfo_scan_mmu_setup().
It replaces the existing mmu_disable() implementation with the assembly
version from coreboot which handles certain edge cases better (see
CB:27238 for details).
The SCTLR flag definitions in libpayload seem to have still been
copy&pasted from arm32, so replace with the actual arm64 defintions from
coreboot.
Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'payloads/libpayload/arch/arm64/cpu.S')
| -rw-r--r-- | payloads/libpayload/arch/arm64/cpu.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/payloads/libpayload/arch/arm64/cpu.S b/payloads/libpayload/arch/arm64/cpu.S index d80f73c112..70a1044b02 100644 --- a/payloads/libpayload/arch/arm64/cpu.S +++ b/payloads/libpayload/arch/arm64/cpu.S @@ -29,6 +29,7 @@ */ #include <arch/asm.h> +#include <arch/lib_helpers.h> .macro dcache_apply_all crm dsb sy @@ -96,3 +97,17 @@ ENDPROC(dcache_clean_all) ENTRY(dcache_clean_invalidate_all) dcache_apply_all crm=cisw ENDPROC(dcache_clean_invalidate_all) + +/* This must be implemented in assembly to ensure there are no accesses to + memory (e.g. the stack) in between disabling and flushing the cache. */ +ENTRY(mmu_disable) + str x30, [sp, #-0x8] + mrs x0, sctlr_el2 + mov x1, #~(SCTLR_C | SCTLR_M) + and x0, x0, x1 + msr sctlr_el2, x0 + isb + bl dcache_clean_invalidate_all + ldr x30, [sp, #-0x8] + ret +ENDPROC(mmu_disable) |