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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-02-29 00:32:23 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-04 10:38:05 +0000
commit4af0adb443afaed32369fe7a9eb91ff93549ea26 (patch)
treeb9209c9ff8309288b0f44f510656076b804684ff /payloads/libpayload/arch/arm/cache.c
parentfdccfc62676719ff4fa09c9aa485a96fa7e818f7 (diff)
soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
update SerialIoUartAutoFlow settings for Tiger Lake platform. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/arm/cache.c')
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