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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-23 22:02:20 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-09-23 06:31:48 +0000
commit85610d8d86de10cdb8c82b61290501ee0b3cf742 (patch)
tree06e8e073dd06f153443a461d1dc5c61bc1d202bd /payloads/external
parent74da5f1e7451c80b8a8420dc79d825074c6ca823 (diff)
soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
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