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author | Katherine Hsieh <Katherine.Hsieh@quantatw.com> | 2017-05-03 19:05:06 +0800 |
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committer | Martin Roth <martinroth@google.com> | 2017-05-05 22:44:16 +0200 |
commit | 8caf8a23f93c5bc135133f257169116221f4f697 (patch) | |
tree | e5599baea183ec9fd95e7657a8d47fcafe8eb046 /payloads/external | |
parent | 915a4cadf48aff628b7a0e472ccfbe9284fafd5a (diff) |
mainboard/google/sand: Update DPTF parameters provided from thermal team
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'payloads/external')
0 files changed, 0 insertions, 0 deletions