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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-01 22:28:03 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-10-28 21:28:19 +0000
commit310c7637daba6ba4e9249928e5cd0e45ef4661e1 (patch)
tree43416b3a09fd9130976254cb1317c47c80c08516 /payloads/external
parent72e49cef806467a16d4d57858ad38b092c0a61ad (diff)
soc/intel: deduplicate ACPI timer emulation
The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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