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authorFurquan Shaikh <furquan@google.com>2019-02-12 08:15:47 -0800
committerFurquan Shaikh <furquan@google.com>2019-02-13 18:46:39 +0000
commit32bc1dc531712e187f830d84e6b03e8b8f5ed936 (patch)
treeaae6e8a9f4adb2a420d91dcc4891596402a095eb /payloads/external/iPXE
parent883d8215038ccd783bed03b9acf175ec5f55d062 (diff)
mb/google/hatch: Bump up the BIOS region to 28MiB
This change bumps up the BIOS region to 28MiB to use the hole between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only the top 16MiB actually gets memory mapped. Thus, the change ensures that only RW_LEGACY lies in the 12MiB that is not memory mapped. BUG=b:123443737 TEST=Verified that hatch still boots up. Ensured that fmap dump looks correct. Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'payloads/external/iPXE')
0 files changed, 0 insertions, 0 deletions