diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-16 14:25:56 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-01 14:08:46 +0000 |
| commit | 4dfcd7acdc705994cd20c27d5e3edfae31672b64 (patch) | |
| tree | d4675d556ea773af54fcb20eaa2df22bbae3350c /payloads/external/edk2 | |
| parent | afa72ee6842b14ebca7b403961784336c0361fe1 (diff) | |
mb/google/brya/acpi: Save/restore/clear some registers over GC6
Nvidia recommends saving and restoring the LTR Enable bit in PCIe config
space for the PCIe root port before/after GC6 entry. Also the detectable
error bit should be cleared, as there may be errors expected during the
GC6 flow.
BUG=b:214581763
TEST=no more correctable errors after GC6 entry/exit
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'payloads/external/edk2')
0 files changed, 0 insertions, 0 deletions