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author | Gaggery Tsai <gaggery.tsai@intel.com> | 2019-12-05 11:23:20 -0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-13 09:05:20 +0000 |
commit | 12a651c060963ed89b46db6b00195874419417ca (patch) | |
tree | 1dfa70693d9f039b2be0101f280fcc34aeb5bf1d /payloads/external/SeaBIOS/Makefile | |
parent | d1613f5681f17c02e5219342a0edc39e4aed685d (diff) |
soc/intel/common: Add PCI device IDs for CMP-H
This patch adds PCI device IDs for CMP-H.
TEST=build coreboot.rom and boot to the OS
Change-Id: Ia7413f75757c64b389a39d6e171f88eb61036c58
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'payloads/external/SeaBIOS/Makefile')
0 files changed, 0 insertions, 0 deletions