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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-05 15:03:50 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-09-13 21:53:27 +0200 |
| commit | 0650cd0bad2816886745c4a7ffe0e7a1aefb9957 (patch) | |
| tree | 5db1d13c75167c0203bcaa0d139a446ad2004772 /payloads/external/SeaBIOS/Makefile.inc | |
| parent | 76998336aa82b692c1b0cf1e2427602b5b655fac (diff) | |
southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash
but address map limits this to 16MiB.
Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'payloads/external/SeaBIOS/Makefile.inc')
0 files changed, 0 insertions, 0 deletions