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authorSubrata Banik <subratabanik@google.com>2022-08-23 02:27:58 +0530
committerSubrata Banik <subratabanik@google.com>2022-08-26 04:13:10 +0000
commit6f7875fb565f87ca6f9e423af60e2d5516f20ea6 (patch)
tree620b0be9905d464648e9f0e0825cd287ea6e439c /payloads/external/SeaBIOS/Kconfig
parent199b10fc21ee094af88abb2b5856502565c40ae7 (diff)
soc/intel/p2sb: Refactor `p2sb_execute_sideband_access` function
This patch refactors p2sb_execute_sideband_access() to be able to handle SBI operations in both SMM and non-SMM scenarios. Prior to FSP-S operation being done, the IOE P2SB device will be visible on the PCI bus hence, performing the SBI operation using IOE P2SB doesn't involve unhide/hide operation. Post FSP-S, the IOE P2SB device is hidden. Additionally, SBI operations can't be performed as is. The only possible way to send SBI is inside SMM mode and to do that, coreboot needs to unhide the P2SB device prior to sending the SBI and hide it post sending SBI. As a result, the p2sb_execute_sideband_access() function has been refactored to manage these cases seamlessly without users of the p2sb_execute_sideband_access() actually being bothered about the calling mode. BUG=b:239806774 TEST=Able to perform p2sb_execute_sideband_access() function call in both SMM and non-SMM mode without any hang/die. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'payloads/external/SeaBIOS/Kconfig')
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