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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 10:25:04 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-24 11:27:51 +0000 |
| commit | 291b58f06e4d9472fa2b8b8ace5b7829fe625d45 (patch) | |
| tree | 11fa36a0866f6969f2a546a9892a3ca084b85655 /payloads/coreinfo | |
| parent | aed1952f059baf71d5584b9a39ca31b3eebc7797 (diff) | |
soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.
Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'payloads/coreinfo')
0 files changed, 0 insertions, 0 deletions