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| author | Caveh Jalali <caveh@chromium.org> | 2020-08-27 02:51:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-31 06:38:53 +0000 |
| commit | d7468bfb27033964e5a23e78b4c9d4b6dc952c00 (patch) | |
| tree | 440080a5cc16c4a3aaa5a7df972c95e2a2c13618 /payloads/coreinfo/coreinfo.h | |
| parent | 551216a4d1a52a56a9de4859873694cbcb0e6109 (diff) | |
xhci: Do not set the CRCR_CS bit
We do not need to set the CS (Command Stop) bit in the Command Ring
Control Register. CS is implied by CA (Command Abort). I'm not sure if
there is a defined execution order for these command bits, so it's
safer to only use the CA bit as it includes the CS function.
Ref: xHCI spec 1.2 (May 2019), Section 5.4.5, Table 5-24.
BUG=b:160354585,b:157123390
TEST=able to boot into recovery using USB stick on servo v2 on volteer
as well as HooToo 8-1 hub
Change-Id: Iaeba98b6da8da49f529358ca6d68270440ea0f42
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'payloads/coreinfo/coreinfo.h')
0 files changed, 0 insertions, 0 deletions