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authorSridhar Siricilla <sridhar.siricilla@intel.com>2023-01-10 16:16:57 +0530
committerMartin L Roth <gaumless@gmail.com>2023-01-15 01:58:17 +0000
commit2e6c55946c4d4ff04e1bc8de7272a4cef63ed55d (patch)
tree1e590896a2a3e5a003e3fd1450b2baf8cc0193e9 /payloads/coreinfo/coreinfo.h
parentdd7d51d12f4cc305ba3d211468f23563acd1f6f1 (diff)
soc/intel/common: Use 'enum cb_error' values
The patch uses 'enum cb_error' values as return values for below functions: 1. cse_get_rw_rdev() 2. cse_erase_rw_region() 3. cse_write_rw_region() 4. cse_locate_area_as_rdev_rw() 5. cse_get_target_rdev() 6. cse_copy_rw TEST=Build, boot and perform CSE downgrade test on the Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'payloads/coreinfo/coreinfo.h')
0 files changed, 0 insertions, 0 deletions