soc/amd/picasso: Enable cache in bootblock

Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM
setup code to properly enable MTRRs.  Add that capability to the
bootblock_c_entry() function.  In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.

BUG=b:147042464
TEST=Boot trembyle to payload and make sure bootblock isn't abnormally
slow.

Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions