diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-02-12 14:17:15 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-14 02:00:10 +0100 |
| commit | 4aff4458f58398f54c248604694c7005294c1747 (patch) | |
| tree | eb3d9259255abc486a4d6d9eb53199b4d408053e /documentation | |
| parent | dc8259ce1d2e866f3133da49c1d6f4773f5698c1 (diff) | |
sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'documentation')
| -rw-r--r-- | documentation/Kconfig.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/documentation/Kconfig.tex b/documentation/Kconfig.tex index e8e3f414e7..1739c05a96 100644 --- a/documentation/Kconfig.tex +++ b/documentation/Kconfig.tex @@ -163,7 +163,7 @@ Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason i is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many BIOSes) that the BSP be CPU 0; any CPU will do. \begin{verbatim} - device pci_domain 0 on + device domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 @@ -338,7 +338,7 @@ That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much he \end{verbatim} \begin{verbatim} - end #pci_domain + end # domain # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all |