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authorDaisuke Nojiri <dnojiri@chromium.org>2014-11-12 14:44:13 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-15 21:55:24 +0200
commit81193e6cd82b464aece48f35e45fae8742114cee (patch)
treecd388c60e9dce910ed5855fa822b503fe58084d6 /documentation/AMD-S3.txt
parentb508a858b562786f064869bd25d376c15aba36dd (diff)
storm: add code for detecting rec/dev/write protect switches' status
The gpio access code has been moved to a separate file to match other platforms. Accessor functions are added to read different switches state. They will be read by verstage, when it is enabled, and by ramstage, for passing the values to depthcharge. It is unfortunate that the gpio values are not being cached and can change by the time CBMEM table is filled, but we have to live with that for now. BUG=chrome-os-partner:33756,chrome-os-partner:34161 BRANCH=storm TEST=none yet. Change-Id: I229fed0e35d643912f929671d5fc25aee5d1d167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e15aa281a1dbf2c463650b6c04991436022d8d4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I940b54cd3cf046b94d57d59d370e634a70a8bbeb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229426 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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