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authorUwe Poeche <uwe.poeche@siemens.com>2022-04-04 15:10:28 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-04-06 16:20:27 +0000
commite9b417c0a0fed113e4254510513f847ec56b5bb3 (patch)
treef5a35f2323c9b7fc5c0da8179d1b0350814396c0 /configs
parentca74d7e65b9562e4d84079af3583524d9e82460f (diff)
soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
This patch provides the set value for intel speed step in devicetree for FSPS. Before that in case of not set value in device tree the default value of disabled was overwritten by default enabled of FSP. Test: mainboard/siemens/mc_ehl/variants/mc_ehl1 Check status of Bit 16 in MSR 0x1a0 after boot. Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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