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author | Raul E Rangel <rrangel@chromium.org> | 2021-06-30 14:39:29 -0600 |
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committer | Raul Rangel <rrangel@chromium.org> | 2021-07-02 23:12:34 +0000 |
commit | 35e27b34f5c9cbab2044a47bf2d6a025ccf7948e (patch) | |
tree | a2d8869f95533a778407f647769cf2923520b3e2 /configs/config.pcengines_apu3 | |
parent | 9942af2b5be306260085289189cb34c8086de733 (diff) |
soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.
BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.
Also boot Ezkinil and verify microcode was also updated.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'configs/config.pcengines_apu3')
0 files changed, 0 insertions, 0 deletions