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authorSridhar Siricilla <sridhar.siricilla@intel.com>2020-12-04 02:22:28 +0530
committerFurquan Shaikh <furquan@google.com>2020-12-14 18:42:12 +0000
commit1a2b70284895a9daef667aada307405039dc8cce (patch)
tree0bca23d18f0d45e664a5e8967714183c7153ace9 /configs/config.libretrend_lt1000
parent4c2890d47ef03e5c638a9ac81d14cf3755f64cfc (diff)
soc/intel/common: Move CSE Lite driver functionality into romstage
The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggers CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM initialization as HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) is expected to be executed after DRAM initialization. With this change, it improves the cold boot time by ~154ms. Test=Verified on JSL and TGL platforms BUG=b:174694480 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.libretrend_lt1000')
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