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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-21 18:47:46 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 22:57:29 +0000 |
commit | 8256ca0e14e57b17b27a81b16f220c94d728e117 (patch) | |
tree | b1bf3a14aa5509c6105d7a7af09e7181f26a6b2b /configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs | |
parent | 3c1e986119cdfece27e5bf953576fa01882bb773 (diff) |
soc/intel/braswell: Update microcode before FSP
The google FSP Braswell version has broken microcode update code and
FSP checks at some point if the installed microcode version is non
zero, so coreboot has to update it before calling FSP-T.
This is fixed with newer FSP releases by Intel, but doing updates in
coreboot won't hurt.
Tested with both Intel FSP and google FSP.
Change-Id: I3e81329854e823dc66fec191adbed617bb37d649
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs')
0 files changed, 0 insertions, 0 deletions