summaryrefslogtreecommitdiff
path: root/configs/config.intel_galileo_gen2.vboot
diff options
context:
space:
mode:
authorzhaojohn <john.zhao@intel.com>2022-10-25 12:38:20 -0700
committerSubrata Banik <subratabanik@google.com>2022-11-02 06:50:12 +0000
commit80a3b9659325bbefa9403f96ecae9303df347b79 (patch)
tree578ae9c08421d7afcb4a25e1251262e53fe24d20 /configs/config.intel_galileo_gen2.vboot
parentb5d402e3886296261eb6134a3f8905c29c7f98c0 (diff)
mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
Rex board only uses TBT PCIe root ports 0 and 2. This change disables rp1 and rp3 root ports. BUG=b:254207628 TEST=Booted to OS and verified rp1 and rp3 root ports were disabled. Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'configs/config.intel_galileo_gen2.vboot')
0 files changed, 0 insertions, 0 deletions