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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-03-18 10:23:26 +0800 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-19 17:43:18 +0000 |
| commit | 34473ea6c9ee63de46b04b46cc47ef4aa5bae2b7 (patch) | |
| tree | b58d446167f4a033ae773287f2b7fd8f13b540a2 /configs/config.intel_galileo_gen2.sd | |
| parent | e82b02c004e94c4f6016543088f99120be415ff3 (diff) | |
soc/intel/xeon_sp: Modify FSP-T code caching parameters
Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching
parameters.
Tested on OCP Tioga Pass.
Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.intel_galileo_gen2.sd')
0 files changed, 0 insertions, 0 deletions