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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-12-31 11:43:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:28:51 +0000 |
| commit | f8248f38a10c6dc664b043445233c8f69c3af0f6 (patch) | |
| tree | a2d700007dc43c09fa8878f21750eb39065e3140 /configs/config.intel_galileo_gen2.debug | |
| parent | de2ab41fc43152b652af7c1f658b1c27926afd6c (diff) | |
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'configs/config.intel_galileo_gen2.debug')
0 files changed, 0 insertions, 0 deletions