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author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-19 18:11:46 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 17:40:38 +0000 |
commit | 98391baf3bef478f3739875f33c09f1c00f5892f (patch) | |
tree | 52a0f9cb521a17325a28b2259519bc7e468ce8bf /configs/config.google_reef_cros | |
parent | b2394e853bf7652fa70295d34892a8385b9a5153 (diff) |
soc/amd/mendocino: clean up global NVS
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.google_reef_cros')
0 files changed, 0 insertions, 0 deletions