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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-07-22 00:48:37 -0600 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-26 05:30:48 +0000 |
| commit | 4c569b52f6053fc39cb07eed4a0753ade567c5b6 (patch) | |
| tree | a7a346600b747651c9af5f0bb53a23fa6ff63b3f /configs/config.google_guado.pch_serialio_uart | |
| parent | 9b6a3a0370ef310c36d5457e8cb0bb752a8418e8 (diff) | |
soc/intel/common/block/gpio: Add support to program VCCIO selection
Some of the Intel SoCs with more than 2 PAD configuration registers
support programming VCCIO selection. Add a pad configuration macro to
program VCCIO selection when the GPIO is an output pin.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.google_guado.pch_serialio_uart')
0 files changed, 0 insertions, 0 deletions