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| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-23 19:29:24 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-25 06:17:54 +0000 |
| commit | a8ddc89d27ed72cf328ef82f5f3c0bdbe6b9f7f1 (patch) | |
| tree | a8052e4bb29672393e5d2da67d8364cb83ae62b2 /configs/config.emulation_qemu_riscv_rv64 | |
| parent | da59ca94cf8004d225edfc07103d06d1beaf2fc1 (diff) | |
vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432
List of changes:
1. FSP-M Header:
- Add new UPD GpioOverride
- Change help text for PlatformDebugConsent UPD
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust Reservedxx UPD Offset
- PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew
by 4 elements
Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.emulation_qemu_riscv_rv64')
0 files changed, 0 insertions, 0 deletions