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authorYuchi Chen <yuchi.chen@intel.com>2024-11-06 08:50:00 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-11-19 10:32:38 +0000
commit26be949137e6ba7e5cf70b668731e7ef219ec283 (patch)
treec9abc707c8674a5f128d8eba1031bbad36a16893 /configs/builder
parent92f90bcd969c1d57b7df16433016b3c2d53784aa (diff)
soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning PIRQ for a given device and INT pin. Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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