cpu/x86/mtrr: Optimize hole carving strategy

For WB ranges with unaligned end, we try to align the range up and
carve a hole out of it which might reduce MTRR usage. Instead of
trying an arbitrary alignment, we try all and choose an optimal
one.

Also, restructure the cases when we try to find a hole. Which leads
us to the following three:

  1. WB range is last in address space:
     Aligning up, up to the next power of 2, may gain us something.

  2. The next range is of type UC:
     We may align up, up to the _end_ of the next range. If there
     is a gap between the current and the next range, it would
     have been covered by the default type UC anyway.

  3. The next range is not of type UC:
     We may align up, up to the _base_ of the next range. This is
     the end of the gap, if there is one.

Change-Id: Iefb064ce8c4f293490a19dd46054b966c63bde44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

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